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MVE™ System-on-Chip |
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Embedded System-on-Chip Video Analytics Solution in Low-cost Spartan FPGAs
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The Multi-core Video Analytics Engine (MVE™) is an easily
configurable, compact, high-performance processing architecture
that can be used to implement complete video analytics solutions
in a single FPGA embedded in intelligent surveillance cameras.
MVE™ System-on-Chip (SoC) combines an inherently parallel
multi-core processing architecture, and embedded complex video
analytics algorithms in a configurable building block, simplifying
hardware design and programming effort resulting in reduced
development cost and time to market.
Embedded solutions also benefit from low-cost and low-power
implementation when embedding the entire MVE™ into a single
FPGA. This initial commercial implementation of MVE™ is on the
Xilinx Spartan-3A DSP 3400A™ FPGA chip.
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MVE™ SoC Implementation Statistics:
MVE™ is currently implemented in a Xilinx Spartan-3A DSP
3400A™ FPGA within a System-on-Chip (SoC) reference
design with all required I/O functions for communication and
data streaming (see block diagrams). The entire SoC solution
uses 98% of the logic slices, 92% of the block RAMs and 42% of
the DSP slices. The MVE™ analytics engine itself (excluding
the MPMC-PLB part of the backbone and specialized I/O
components) utilizes only 46% of the logic slices, 31% of the
block RAMs and 30% of the DSP slices.
Key MVE™ Features:
- Stand-alone configurable Video Analytics engine based on
high-performance C-MVA™ processor architecture
- Fully configurable VA functions such as people counting,
detection of abandoned/stolen objects, entering forbidden
zone, loitering, movement in wrong direction
- Enables single-chip VA solution in Xilinx FPGAs
Image capture and video analysis done in HD image
resolution at 30 frames per second
- Arbitrary number of events detected in parallel
- Pixel processing and acceleration implemented by parallel
IP cores
- Reference design and evaluation kit available for the
Eutecus Bi-i™ V401X VA platform and the Xilinx
XtremeDSP™ Video Starter Kit (VSK)
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MVE™ System-on-Chip

MVE™ Algorithmic Structure

MVE™ Backbone Architecture

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MVE™ IP Core Information |
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on Spartan-3A DSP based Xilinx VSK & Eutecus Bi-i™ V40X Platforms
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| Core format | EDIF netlist, VHDL instantiation template, MicroBlaze or PPC libraries |
| Principal (algorithmic) modules | Image flow scaling and windowing; Statistical analysis; Image flow conditioning and noise
filtering; Foreground-background separation; Binary morphological filtering; Signature and
feature extraction; Multi-target tracking; Signature/feature analysis and Event
detection/classification |
| Digital video formats supported | 4:2:2 YCrCb (16-bit) & 4:4:4 RGB (24-bit)
Bayer pattern (Directly from sensor)
Monochrome (8-bit) |
| Synchronization | Auto-synchronized to the incoming video flow |
| Video input standards | SDTV (VGA 640x480, NTSC 720x480, PAL 720x576), HDTV (720p-no scaling, 1080p-with scaling) |
| Supported input frame resolution | Up to 1024x1024 (no scaling); up to 2048x2048 (with scaling) |
| Processed frame resolution | Up to 1024 pixels/line (number of lines is not restricted)
For larger resolution windowing and/or downscaling is applied |
| Pipeline delay (latency) | 2 video frames |
| External memory | Minimum 1 input frame +
(processed frame size) x 2 bytes +
4 Mbytes program & data storage |
| Parameter Control | RS232 serial, Ethernet The core is fully programmable via PC GUI |
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Embedding MVE™ in OEM Security Cameras
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The diagrams show the main components and interfaces of MVE™ System-on-Chip (SoC) as well as the software layers that
used for integrating MVE™ into OEM cameras and other devices with embedded video analytics capability.
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Go to the main MVE™ page
Download the MVE™ SoC Datasheet Brief in
PDF
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